Such a method is described in, for example, U.S. Pat. No. 4,641,420 and Japanese Patent application JP-A-60124951. As described in Japanese Patent application JP-A-60124951, the spaced-apart regions are electrically conductive regions formimg part of a metallisation level and, after anisotropic etching of the insulating material to leave portions or spacers of the insulating material on the side walls of the electrically conductive regions, a further insulating layer is provided over the electrically conductive regions to protect the electrically conductive regions from corrosion and/or oxidation. In contrast, U.S. Pat. No. 4,641,420 describes a method of contacting an underlying region such as a doped zone adjacent a surface of a semiconductor body by opening a via through insulating material provided over the surface of the semiconductor body so that the via forms the spaced-apart regions between which the surface of the doped zone is exposed. A layer of insulating material provided over the spaced-apart regions is etched anisotropically to leave portions or spacers of the insulating material on the side walls of the spaced-apart regions. An electrically conductive layer is then deposited to make electrical contact to the doped zone.
In both U.S. Pat. No. 4,641,420 and Japanese Patent application JP-A-60124951, the aim of providing the spacers or portions of insulating material on the side walls of the spaced-apart regions is to provide a more smooth surface, that is a surface with less steep side walls and sharp steps or corners, onto which a subsequent layer can be deposited so that the underlying surface structure does not cause undesired weaknesses or breaks in the subsequent layer. However, the surface provided by the spacers or portions of the insulating material remaining on the side walls of regions can be quite steep and indeed near the intersection of a spacer with the surface the surface provided by the spacer can be almost perpendicular to the surface of the substructure. Although the use of the methods described above enables satisfactory coverage by the further layer when the spacing between the regions is relatively large in comparison to the thickness of the regions, where the spacing of the regions is comparable to the thickness of the regions (that is the height of the side walls) then problems with coverage by the subsequent layer may occur because of, for example, the relatively steep surface provided by the spacers at the intersection with the surface of the substrate.
It is an object of the present invention to provide a method of manufacturing a semiconductor device which aims at enabling spacers or portions of insulating material to be provided on the side walls so that the surface provided by the spacers has a relatively more gentle slope so that the steps and edges over which a subsequent layer is to be provided are relatively less steep and sharp.